1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a structure for protecting a MOS transistor formed on a silicon-on-insulator (SOI) substrate from an overcurrent caused by static electricity or the like.
2. Description of the Related Art
In a semiconductor integrated circuit device including a resistor circuit composed of a resistor made of polysilicon or the like, an input or output protection element made of a diode or a MOS transistor is generally disposed between an internal circuit and an external input/output terminal to prevent breakdown of internal elements composing the internal circuit when an excess amount of current of a standard value or more flows into the circuit from outside by static electricity or the like.
FIGS. 2A to 2C show examples of an input/output circuit unit in a conventional semiconductor integrated circuit device having such protection circuits. In FIG. 2A, a CMOS inverter 11 composed of an N-channel MOS transistor and a P-channel MOS transistor is illustrated as an internal element 10 of a CMOS structure. N-channel MOS transistors are provided as protection elements 20 between the CMOS inverter 11 and both an input terminal 301 and an output terminal 302, and between a Vdd line 303 and a Vss line 304. Note that the circuit configuration of the internal element is illustrated as the CMOS inverter 11 for ease of explanation.
With the above configuration, application of a negative overvoltage to the input or output terminal, for example, makes a forward voltage to attain at a PN junction of one of the NMOS transistors of the protection elements 20, causing a current flow in the protective NMOS transistor to protect the internal element. In contrast, when a positive overvoltage is applied, a current flows into the protective NMOS transistors by avalanche breakdown at the PN junction of the NMOS transistor in the protection elements 20. In this way, an overcurrent is directly guided to a grounded substrate by way of the input/output protection element and is thus kept from flowing in the internal element.
Input/output protection for the NMOS transistor 113 composing the internal element 10 shown in FIG. 2B and that for a PMOS transistor 112 composing the internal element 10 with a PMOS structure shown in FIG. 2C are directed to electrostatic discharge (ESD) protection in the same manner.
In general, a device element formed on an SOI substrate, particularly on a thin-film SOI substrate, is surrounded by a buried insulating film and an isolation insulating film, and thus exhibits poor heat dissipation performance and is likely to break down by heat generation due to an overcurrent. Therefore, an SOI device has a structure which is significantly vulnerable to ESD. When an ESD protection element is formed on the SOI semiconductor thin film to protect an inner circuit, the heat generation due to the overcurrent also causes the protection element to easily break down. In view of the above, various schemes have been implemented to obtain sufficient ESD strength.
For example, in a semiconductor integrated circuit device where a CMOS buffer ESD protection circuit is formed on an SOI substrate as an input protection element for an internal element, a PNP or NPN diode is additionally provided in front of the CMOS buffer ESD protection circuit to enhance the ESD strength (see JP 3447372 B (p. 6, FIG. 2), for example).
As mentioned above, the formation of the ESD protection element on the SOI substrate involves enlarging the protection element or increasing the number of protection elements for attaining a sufficient ESD strength, and is disadvantageous in that the protection circuit area and chip area are extended.
Meanwhile, as one way to attain the sufficient ESD strength, JP 04-345064 A (p. 9, FIG. 1) and JP 08-181219 A (p. 5, FIG. 1) disclose a semiconductor integrated circuit device in which an internal element 10 is formed in an SOI semiconductor thin film and an input protection element is formed on a semiconductor support substrate.
However, when the semiconductor thin film or buried insulating film of the SOI substrate is partially removed to expose the semiconductor support substrate and the protection element is formed on the exposed portion, the protection element itself can secure a sufficient ESD strength, but a problem arises in that the internal element cannot be sufficiently protected.
This is caused by the following mechanism. That is, in a general circuit design, an incoming ESD noise is supposed to get out through the ESD protection element in advance to the internal element. However, large withstand voltage of the ESD protection element on the semiconductor support substrate prevents the protection element from reacting to the ESD noise introduced from the output terminal 302, and the noise enters the internal element on the SOI semiconductor thin film, resulting in the breakdown of the internal element. Accordingly, the starting voltage of the ESD protection operation should be lower than the withstand voltage of the internal element while the ESD protection element on the semiconductor support substrate is designed to ensure sufficient breakdown strength.